250 lines
8.2 KiB
C++
250 lines
8.2 KiB
C++
/***************************************************************************************************
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification, are permitted
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* provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright notice, this list of
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* conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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* * Neither the name of the NVIDIA CORPORATION nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NVIDIA CORPORATION BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TOR (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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**************************************************************************************************/
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/*! \file
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\brief Architecture-specific operators on memory added for SM80
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*/
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#pragma once
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#include "cutlass/cutlass.h"
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#include "cutlass/arch/memory_sm75.h"
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#include "cutlass/arch/cache_operation.h"
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#if defined(__CUDA_ARCH__) && (__CUDA_ARCH__ >= 800)
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#define CUDA_CP_ASYNC_ACTIVATED 1
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#else
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#define CUDA_CP_ASYNC_ACTIVATED 0
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#endif
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namespace cutlass {
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namespace arch {
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////////////////////////////////////////////////////////////////////////////////////////////////////
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/// Initiates an asynchronous copy from global memory to shared memory.
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///
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/// LDGSTS
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///
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template <
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/// Size of the access in bytes
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int SizeInBytes,
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/// Cache operation
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CacheOperation::Kind cache_op = CacheOperation::Always>
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struct cp_async;
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/// Initiates an asynchronous copy from global memory to shared memory. Rather than predicate
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/// the entire transfer, zeros are written to SMEM if the guard predicate is false.
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///
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/// LDGSTS
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///
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template <
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/// Size of the access in bytes
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int SizeInBytes,
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/// Cache operation
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CacheOperation::Kind cache_op = CacheOperation::Always>
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struct cp_async_zfill;
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////////////////////////////////////////////////////////////////////////////////////////////////////
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/// Partial specialization
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template <
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/// Size of the access in bytes
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int SizeInBytes>
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struct cp_async<SizeInBytes, CacheOperation::Always> {
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/// Copy
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CUTLASS_DEVICE
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cp_async(void *smem_ptr, void const *global_ptr, bool pred_guard = true) {
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#if CUDA_CP_ASYNC_ACTIVATED
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// Make sure the size is supported.
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static_assert((SizeInBytes == 4 || SizeInBytes == 8 || SizeInBytes == 16),
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"Size is not supported");
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unsigned smem_int_ptr = cutlass_get_smem_pointer(smem_ptr);
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asm volatile(
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"{\n"
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" .reg .pred p;\n"
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" setp.ne.b32 p, %0, 0;\n"
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" @p cp.async.ca.shared.global [%1], [%2], %3;\n"
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"}\n" ::"r"((int)pred_guard),
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"r"(smem_int_ptr), "l"(global_ptr), "n"(SizeInBytes));
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#else
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using AccessType = Array<uint8_t, SizeInBytes>;
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if (pred_guard) {
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*static_cast<AccessType *>(smem_ptr) = *static_cast<AccessType const *>(global_ptr);
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}
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#endif
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}
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};
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/// Partial specialization
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template <
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/// Size of the access in bytes
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int SizeInBytes>
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struct cp_async_zfill<SizeInBytes, CacheOperation::Always> {
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/// Copy with zero fill
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CUTLASS_DEVICE
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cp_async_zfill(void *smem_ptr, void const *global_ptr, bool pred_guard) {
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#if CUDA_CP_ASYNC_ACTIVATED
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// Make sure the size is supported.
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static_assert((SizeInBytes == 4 || SizeInBytes == 8 || SizeInBytes == 16),
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"Size is not supported");
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unsigned smem_int_ptr = cutlass_get_smem_pointer(smem_ptr);
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int src_in_bytes = (pred_guard ? SizeInBytes : 0);
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asm volatile(
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"cp.async.ca.shared.global [%0], [%1], %2, %3;\n" ::"r"(smem_int_ptr),
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"l"(global_ptr), "n"(SizeInBytes), "r"(src_in_bytes));
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#else
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using AccessType = Array<uint8_t, SizeInBytes>;
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if (pred_guard) {
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*static_cast<AccessType *>(smem_ptr) = *static_cast<AccessType const *>(global_ptr);
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}
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else {
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AccessType zeros;
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zeros.clear();
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*static_cast<AccessType *>(smem_ptr) = zeros;
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}
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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/// Partial specialization
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template <
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/// Size of the access in bytes
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int SizeInBytes>
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struct cp_async<SizeInBytes, CacheOperation::Global> {
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/// Copy
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CUTLASS_DEVICE
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cp_async(void *smem_ptr, void const *global_ptr, bool pred_guard = true) {
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#if CUDA_CP_ASYNC_ACTIVATED
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static_assert(SizeInBytes == 16,
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"cp.async only supports CacheOperation::Global when access size is 16B.");
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unsigned smem_int_ptr = cutlass_get_smem_pointer(smem_ptr);
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asm volatile(
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"{\n"
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" .reg .pred p;\n"
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" setp.ne.b32 p, %0, 0;\n"
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" @p cp.async.cg.shared.global [%1], [%2], %3;\n"
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"}\n" ::"r"((int)pred_guard),
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"r"(smem_int_ptr), "l"(global_ptr), "n"(SizeInBytes));
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#else
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using AccessType = Array<uint8_t, SizeInBytes>;
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if (pred_guard) {
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*static_cast<AccessType *>(smem_ptr) = *static_cast<AccessType const *>(global_ptr);
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}
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#endif
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}
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};
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/// Partial specialization
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template <
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/// Size of the access in bytes
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int SizeInBytes>
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struct cp_async_zfill<SizeInBytes, CacheOperation::Global> {
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/// Copy with zero fill
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CUTLASS_DEVICE
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cp_async_zfill(void *smem_ptr, void const *global_ptr, bool pred_guard = true) {
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#if CUDA_CP_ASYNC_ACTIVATED
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static_assert(SizeInBytes == 16,
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"cp.async only supports CacheOperation::Global when access size is 16B.");
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unsigned smem_int_ptr = cutlass_get_smem_pointer(smem_ptr);
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int src_in_bytes = (pred_guard ? SizeInBytes : 0);
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asm volatile(
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"cp.async.cg.shared.global [%0], [%1], %2, %3;\n" ::"r"(smem_int_ptr),
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"l"(global_ptr), "n"(SizeInBytes), "r"(src_in_bytes));
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#else
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using AccessType = Array<uint8_t, SizeInBytes>;
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if (pred_guard) {
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*static_cast<AccessType *>(smem_ptr) = *static_cast<AccessType const *>(global_ptr);
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}
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else {
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AccessType zeros;
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zeros.clear();
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*static_cast<AccessType *>(smem_ptr) = zeros;
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}
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#endif
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}
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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/// Establishes an ordering w.r.t previously issued cp.async instructions. Does not block.
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CUTLASS_DEVICE
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void cp_async_fence() {
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#if CUDA_CP_ASYNC_ACTIVATED
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asm volatile("cp.async.commit_group;\n" ::);
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#endif
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}
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////////////////////////////////////////////////////////////////////////////////////////////////////
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/// Blocks until all but <N> previous cp.async.commit_group operations have committed.
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template <int N>
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CUTLASS_DEVICE void cp_async_wait() {
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#if CUDA_CP_ASYNC_ACTIVATED
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asm volatile("cp.async.wait_group %0;\n" ::"n"(N));
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#endif
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}
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/// Blocks until all previous cp.async.commit_group operations have committed.
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template <>
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CUTLASS_DEVICE void cp_async_wait<0>() {
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#if CUDA_CP_ASYNC_ACTIVATED
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asm volatile("cp.async.wait_all;\n" ::);
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#endif
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}
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/////////////////////////////////////////////////////////////////////////////////////////////////
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} // namespace arch
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} // namespace cutlass
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/////////////////////////////////////////////////////////////////////////////////////////////////
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