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9705fba7b7
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[cpu][perf] Accelerate unquantized-linear for AArch64 through oneDNN/ACL and weight prepack (#25948)
Signed-off-by: Fadi Arafeh <fadi.arafeh@arm.com>
Co-authored-by: Li, Jiang <jiang1.li@intel.com>
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2025-10-04 12:16:38 +08:00 |
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359d293006
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[fix]: add Arm 4bit fused moe support (#23809)
Signed-off-by: Nikhil Gupta <nikhil.gupta2@arm.com>
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2025-09-24 01:32:22 +00:00 |
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57b1ce94f7
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[CPU] Refactor CPU unquantized linear (#24150)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-09-04 14:28:45 +08:00 |
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7be5d113d8
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[CPU] Refactor CPU W8A8 scaled_mm (#23071)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-08-21 09:34:24 +08:00 |
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9094d11c5d
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[Bugfix][Apple Silicon] fix missing symbols when build from source on Mac with Apple Silicon (#21380)
Signed-off-by: Yeju Zhou <yejuzhou@outlook.com>
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2025-07-26 07:09:57 -07:00 |
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c7753a9809
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[Hardware][CPU] Vllm int8 quantization enablement for ARM CPU (#14129)
Signed-off-by: nishith-fujitsu <nishith.jaiswal@fujitsu.com>
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2025-07-10 15:59:04 +00:00 |
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6cc1e7d96d
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[CPU] Update custom ops for the CPU backend (#20255)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-07-01 07:25:03 +00:00 |
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0567c8249f
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[CPU] Fix torch version in x86 CPU backend (#19258)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-06-26 03:34:47 -07:00 |
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e515668edf
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[Hardware][Power] Enable compressed tensor W8A8 INT8 quantization for POWER (#17153)
Signed-off-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: Akash Kaothalkar <akash.kaothalkar@ibm.com>
Co-authored-by: mgoin <mgoin64@gmail.com>
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2025-05-07 22:35:03 -07:00 |
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98c89e16ff
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Make key optional for rotary embedding (#17566)
Signed-off-by: Yong Hoon Shin <yhshin@meta.com>
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2025-05-07 00:11:46 -07:00 |
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550b2801ad
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[CPU][Bugfix] Using custom allreduce for CPU backend (#15934)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-04-02 07:46:47 -07:00 |
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4f044b1d67
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[Kernel][CPU] CPU MLA (#14744)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
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2025-03-25 09:34:59 +00:00 |
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e97f802b2d
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[FP8][Kernel] Dynamic kv cache scaling factors computation (#11906)
Signed-off-by: Gregory Shtrasberg <Gregory.Shtrasberg@amd.com>
Co-authored-by: Micah Williamson <micah.williamson@amd.com>
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2025-01-23 18:04:03 +00:00 |
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4068f4b5b5
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[MISC] Replace c10::optional with std::optional (#11730)
Signed-off-by: Lu Fang <lufang@fb.com>
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2025-01-05 10:20:34 +09:00 |
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5eda21e773
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[Hardware][CPU] compressed-tensor INT8 W8A8 AZP support (#9344)
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2024-10-17 12:21:04 -04:00 |
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5d73ae49d6
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[Kernel] AQ AZP 3/4: Asymmetric quantization kernels (#7270)
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2024-09-16 11:52:40 -07:00 |
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73202dbe77
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[Kernel][Misc] register ops to prevent graph breaks (#6917)
Co-authored-by: Sage Moore <sage@neuralmagic.com>
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2024-09-11 12:52:19 -07:00 |
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0b952af458
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[Hardware][Intel] Support compressed-tensor W8A8 for CPU backend (#7257)
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2024-09-11 09:46:46 -07:00 |
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a8d604ca2a
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[Misc] Disambiguate quantized types via a new ScalarType (#6396)
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2024-08-02 13:51:58 -07:00 |
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3bbb4936dc
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[Hardware] [Intel] Enable Multiprocessing and tensor parallel in CPU backend and update documentation (#6125)
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2024-07-26 13:50:10 -07:00 |
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978aed5300
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[Kernel][Attention] Separate Attention.kv_scale into k_scale and v_scale (#6081)
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2024-07-16 15:31:32 -07:00 |
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bd620b01fb
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[Kernel][CPU] Add Quick gelu to CPU (#5717)
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2024-06-21 06:39:40 +00:00 |
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5467ac3196
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[Kernel][Misc] Use TORCH_LIBRARY instead of PYBIND11_MODULE for custom ops (#5047)
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2024-06-09 16:23:30 -04:00 |
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