Li, Jiang a15a50fc17 [CPU] Enable shared-memory based pipeline parallel for CPU backend (#21289) ...

Signed-off-by: jiang1.li <jiang1.li@intel.com>

2025-07-21 09:07:08 -07:00

..

hardware_ci

[CPU] Enable shared-memory based pipeline parallel for CPU backend (#21289)

2025-07-21 09:07:08 -07:00

tpu

[Test] Remove docker build from test. (#20542)

2025-07-10 11:21:58 -07:00

annotate-release.sh

[Build] Annotate wheel and container path for release workflow (#19162)

2025-06-04 23:24:56 -07:00

ci-clean-log.sh

[doc] improve ci doc (#19307)

2025-06-09 07:26:12 +00:00

rerun-test.sh

[doc] improve ci doc (#19307)

2025-06-09 07:26:12 +00:00

run-benchmarks.sh

[CI] Fix benchmark script level (#16089)

2025-04-05 03:36:01 -07:00

run-multi-node-test.sh

[CI] Reorganize .buildkite directory (#16001)

2025-04-04 12:16:20 -07:00

upload-wheels.sh

Upload vllm index for the rc builds (#18173)

2025-05-14 16:35:56 -07:00