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@ -68,7 +68,6 @@ using ElementC = ElementOutput;
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using ElementCompute = ElementComputeEpilogue;
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using LayoutInputA = cutlass::layout::TensorNHWC;
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using LayoutInputB = cutlass::layout::TensorNHWC;
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using LayoutInputScaleBias = cutlass::layout::RowMajor;
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using LayoutOutput = cutlass::layout::TensorNHWC;
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// This code section describes whether you want to use tensor cores or regular SIMT cores on GPU SM
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@ -113,7 +112,7 @@ using EpilogueOpGEMM = cutlass::epilogue::thread::LinearCombination<
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// The epilogue functor for reduction. This is the one that is actually used.
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using EpilogueOpReduction = cutlass::epilogue::thread::LinearCombination<
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ElementOutput, // Data type of output matrix.
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128 / cutlass::sizeof_bits<ElementOutput>::value, // The number of elements per vectorized.
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128 / cutlass::sizeof_bits<ElementAccumulator>::value, // The number of elements per vectorized.
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// memory access. This becomes the vector width of
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// math instructions in the epilogue too.
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ElementAccumulator, // Data type of accumulator
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@ -1,4 +1,4 @@
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# Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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# Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without modification, are permitted
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# provided that the following conditions are met:
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@ -68,7 +68,6 @@ using ElementC = ElementOutput;
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using ElementCompute = ElementComputeEpilogue;
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using LayoutInputA = TensorNHWC;
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using LayoutInputB = TensorNHWC;
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using LayoutInputScaleBias = cutlass::layout::RowMajor;
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using LayoutOutput = TensorNHWC;
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// This code section describes whether you want to use tensor cores or regular SIMT cores on GPU SM
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@ -1,4 +1,4 @@
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# Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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# Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without modification, are permitted
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# provided that the following conditions are met:
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